Computer systems include devices such as microprocessors, main memory, disk drives, network adaptors, etc., that communicate with each other via data buses. Typical computer systems include a system bus, a memory bus, and a local bus. FIG. 1 is a block diagram illustrating a computer system employing several devices coupled together via a system bus, a memory bus, and a PCI bus. More particularly, FIG. 1 shows a microprocessor 10, cache 12, and PCI bridge/memory controller (hereinafter PCI bridge) 14 coupled together via system bus 16. PCI bridge could be implemented in one or multiple devices. Main memory 20 is also included; however main memory 20 is coupled to PCI bridge 14 via memory bus 22. Additionally, FIG. 1 shows PCI bridge 14 coupled to PCI devices 24, 26, 28 and 30 via PCI bus 32. It is noted that two devices can be coupled together directly or indirectly. For example, PCI device 24 is coupled to PCI device 30.
PCI Local Bus Specifications (including version 2.3) and PCI-X Specifications (including version 2.0) (available at www.pcisig.com) are exemplary, published versions of the PCI bus specification that defines the PCI signaling and protocol characteristics of PCI bridge 14, PCI devices 24-30, and/or PCI bus 32. PCI Local Bus Specifications and PCI-X Local Bus Specifications are incorporated herein by reference in their entirety. For ease of explanation, operational characteristics of PCI bridges, PCI devices, and/or PCI buses will be described herein as components conforming to the signaling and protocol of the latest PCI Local Bus Specification.
PCI bridge 14 is a device well known in the art. PCI bridge 14 is provided as a buffer/translator between PCI bus 32 and system bus 16. The signaling and protocol on the PCI bus 32 (as defined, for example, by a PCI Local Bus Specification) is different than the signaling and protocol on the system bus 16. PCI bridge 14 “bridges” these differences between signaling and protocol so that PCI devices 24, 26, 28 and 30 may communicate with, for example, microprocessor 10, memory 20 or cache 12. In other words, PCI bridge 14 receives and subsequently translates PCI formatted data into data formatted for transmission over system bus 16 and memory bus 22, and vice versa.
FIG. 2 illustrates (in block diagram form) pin requirements for PCI devices 24, 26, 28 and 30 to interface with PCI bus 32 according to PCI Local Bus Specification. FIG. 2 shows that each PCI device requires a minimum of 47 pins for a target only device and 49 pins for a master device to handle data and addressing, interface control, arbitration, and system functions on PCI bus 32. A master device initiates a read or write-data transaction directed to another device. Targeted devices are those to which the read or write-data transactions are directed.
FIG. 2 shows the pins in functional groups, with required pins on the left side and optional pins on the right side. The clock (CLK) provides timing for all read or write transactions on PCI bus 32. Address and data (AD[31::00]) are multiplexed on the same PCI pins. A bus transaction consists of an address phase followed by one or more data phases. It is noted that PCI data bus supports both read and write bursts. The remaining definition of the signals shown in FIG. 2 can be found in PCI Local Bus Specification.
FIG. 3 illustrates, in block diagram form, relevant components of PCI devices 24 and 26. PCI devices 28 and 30 may take similar form. PCI device 24 includes core circuit 40, internal bus 44, and PCI interface 42, while PCI device 26 includes core circuit 50, internal bus 54, and PCI interface 52. PCI interfaces 42 and 52 are circuits coupled between parallel internal buses 44 and 54, respectively, and PCI bus 32.
Respective components in PCI devices 24 and 26 differ in structure and operating characteristics. In other words, core circuits 40 and 50 are substantially different in structure and operating characteristics from each other, internal buses 44 and 54 are substantially different in structure and operating characteristics from each other, and PCI interfaces 42 and 52 are substantially different in structure and operating characteristics from each other. To illustrate, core circuit 40 may take form in one or more components of a graphics controller, while core circuit 50 may take form in one or more components of a universal serial bus (USB) host controller. Data is transmitted back and forth between core circuit 40 and PCI interface 42 using a signaling and protocol unique to bus 44, while data is transmitted back and forth between core circuit 50 and PCI interface 52 using a signaling and protocol unique to bus 54. The signaling for buses 44 and 54 are different from each other. Moreover, the signaling and protocol on internal buses 44 and 54 are different from the signaling and protocol of PCI bus 32. PCI interface 42 translates the difference in signaling and protocol in PCI bus 32 and internal bus 44, while PCI interface 52 translates the difference in signaling and protocol in PCI bus 32 and internal bus 54. In other words, PCI interface 42 translates data received from core circuit 40 in a format for transmission over internal bus 44 into data formatted for transmission over PCI bus 32 and vice versa, while PCI interface 52 translates data received from core circuit 50 in a format for transmission over internal bus 54 into data formatted for transmission over PCI bus 32 and vice versa. The PCI interfaces operate according to the signaling and protocol of PCI Local Bus Specification and enable the core circuits 40 and 50 to communicate with other devices via PCI bus 32. Although the PCI interface circuits 42 and 52 can communicate with PCI bus 32, PCI interface circuit 42 cannot be successfully replaced with the PCI interface circuit 52 or vice versa.
PCI has been successfully used as a local bus in computer systems in the past. However, demands of emerging and future computer systems will exceed the bandwidth and scalability limits that are inherent in PCI bus implementations. PCI-Express bus is a new bus designed to replace the PCI bus and address limitations thereof. PCI-Express bus is also designed as a replacement to the system bus (e.g., system bus 16). However, the present invention will be described with reference to PCI-Express as a replacement to PCI bus.
PCI-Express bus and PCI bus are substantially different. Unlike the PCI bus, the PCI-Express bus is a serial bus, and as such PCI-Express bus employs a reduced number of traces (i.e., conductive lines) for transmitting data between PCI-Express devices. This provides several advantages. The reduction of traces eases the costs of computer systems employing the PCI-Express bus. The reduced number of traces also reduces electromagnetic interference (EMI) and radio frequency interference (RFI) shieldings.
FIG. 4 shows the computer system of FIG. 1 with the PCI bridge 14, PCI devices 24-30, and PCI bus 32 replaced by PCI-Express bridge 58, PCI-Express devices 64-70, and PCI-Express buses 72, respectively. PCI-Express is a point-to-point technology. As such, a separate PCI-Express bus 72 connects PCI-Express bridge 58 to individual PCI-Express devices 64, 66, 68, or 70 as shown. Several versions of PCI-Express Specification define the signaling and protocol characteristics of PCI-Express bridge 58, PCI-Express devices 64, 66, 68 and 70, and/or PCI-Express busses 72. Each version is incorporated herein by reference in its entirety.
Protocol and signaling for the system bus 16 is substantially different than the protocol and signaling for each PCI-Express bus 72. Without PCI-Express bridge 58, PCI devices 64, 66, 68 and 70 could not communicate with, for example, microprocessor 10. PCI-Express bridge 58 acts as a buffer/translator between a PCI-Express device and devices coupled to system bus 16 and memory bus 22. PCI Express bridge 58 translates PCI-Express formatted data into data formatted for transmission over system bus 16 and memory bus 22, and vice versa.
FIG. 5 is a block diagram showing relevant components of PCI-Express devices 64 and 66 coupled to respective PCI-Express buses 72. The PCI-Express devices shown in FIG. 5 are the PCI devices shown in FIG. 3 with the PCI interface circuits 42 and 52 replaced by PCI-Express interface circuits 82 and 92, respectively. PCI-Express interface circuit 82 is substantially different than the PCI interface circuit 42, and PCI-Express interface circuit 92 is substantially different than the PCI interface circuit 52. The signaling and protocol on internal buses 44 and 54 are different from the signaling and protocol of PCI-Express buses 72. PCI-Express interface 82 translates the difference in signaling and protocol in PCI-Express bus 72 and internal bus 44, while PCI-Express interface 92 translates the difference in signaling and protocol in PCI-Express bus 72 and internal bus 54. In other words, PCI-Express interface 82 translates data received from core circuit 40 in a format for transmission over internal bus 44, into data formatted for transmission over PCI-Express bus 72 and vice versa, while PCI-Express interface 92 translates data received from core circuit 50 in a format for transmission over internal bus 54, into data formatted for transmission over PCI-Express bus 72 and vice versa. The PCI-Express interfaces operate according to the signaling and protocol of a PCI-Express Specification and enable the core circuits 40 and 50 to communicate with other devices.
Although the PCI-Express interface circuits 82 and 92 can communicate with PCI-Express bus 72, PCI-Express interface circuit 82 cannot be successfully replaced with the PCI-Express interface circuit 92 or vice versa. Accordingly, each PCI interface circuit (or class of PCI interface circuits) of PCI devices 24, 26, 28 and 30 must be replaced with a unique PCI-Express interface circuit in order to successfully transform PCI devices 24, 26, 28 and 30 into PCI-Express devices 64, 66, 68 and 70, respectively. The time and cost for designing these replacement PCI-Express interface circuits may impede the manufacture and sale of computer systems such as that shown in FIG. 4. And the time and cost for designing these replacement PCI-Express interface circuits may impede the manufacture and sale of PCI Express devices such as that shown in FIG. 4.